Cell Architecture for Nanoelectronic Design

TL;DR

This paper proposes a cell architecture for nanoelectronic design that addresses key gate-level challenges, demonstrating improved error tolerance and signal restoration capabilities for nano-scale systems.

Contribution

It introduces a novel cell architecture for nanoelectronics and presents methods to enhance its error tolerance and signal integrity at the gate level.

Findings

Built 2 and 3-input NAND gates with error probability analysis

Demonstrated reduction of output standard deviation by over a factor of √2

Outlined a method to improve device interference tolerance

Abstract

Several nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build medium/large systems. Nanoarchitecture proposals only solve a small part of the problems needed to achieve a real design. In this paper, we propose and analyze a cell architecture that overcomes most of those at the gate level. Using the cell structure we build 2 and 3-input NAND gates showing their error probabilities. Finally, we outline a method to further improve the structure's tolerance by taking advantage of interferences among nanodevices. Using this improvement we show that it is possible to reduce the output standard deviation by a factor larger than $\sqrt{2}$ and restitute the signal levels using nanodevices.