Application of a design space exploration tool to enhance interleaver generation

TL;DR

This paper introduces a methodology that uses a graph-theoretic model and design space exploration tools to automatically generate optimized communication adapters, exemplified by designing an Ultra-Wideband interleaver.

Contribution

It presents a novel framework combining formal modeling and automated exploration to optimize communication architectures in DSP applications.

Findings

Successfully designed an Ultra-Wideband interleaver using the proposed method.

Automated architecture generation reduces design time and improves performance.

The approach effectively balances throughput, latency, and resource constraints.

Abstract

This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). Design space exploration is then performed through associated tools, to synthesize a STAR component under time-to-market constraints. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.